1. Field of the Invention
The present invention relates to a pattern shape evaluation apparatus, a pattern shape evaluation method, a semiconductor device manufacturing method, and a program.
2. Related Background Art
Heretofore, in evaluating a pattern of a semiconductor device, an image of the pattern is acquired, the width of the pattern is measured at an arbitrary place from the obtained image, and the width is compared with a preset specification. However, when the shape of the pattern is complicated, it is impossible to know a change in the whole shape of the pattern if the dimensional measurement is carried out at one place alone. The number of measurement points has to be increased to know the overall change, but this decreases the throughput of the measurement.
In order to solve the above-mentioned problem, there have been proposed various methods for comparing the shape of a pattern with data serving as an evaluation standard. These proposals include a pattern shape evaluation method which comprises: acquiring an image of an actual pattern which is an evaluation target by, for example, a scanning electron microscope (SEM); and acquiring the edge of the evaluation target pattern from the acquired image; superposing this edge on, for example, design data or lithography simulation data for the pattern.
For example, there is a method which comprises: aligning the edge of an evaluation pattern with design data before measuring the distance of a difference therebetween, and evaluating how faithfully to the design data the actual pattern is formed, thereby judging whether the sample is good or bad, and there is also a method which compares the edge of an actual pattern with a lithography simulation result to verify the accuracy of a simulation model. There is another method which comprises: providing in advance an allowable range (tolerance data) in design data; aligning the edge of an evaluation target pattern with the tolerance data to check whether the edge of the evaluation pattern is within the allowable range, thereby judging whether the evaluation target pattern is good or bad. In any of these evaluation methods, the accuracy of aligning (matching) the evaluation target pattern with a reference pattern greatly influences the evaluation.
However, the shape of a pattern on an actual wafer is often distorted with respect to design data, and this cause difficulty in the alignment. Moreover, the degree of the distortion is not uniform among a plurality of patterns present in an acquired image, and unpredictable distortions are also found. For example, there is a case where the position of only one at the end of a plurality of line patterns arranged in parallel to each other has moved from the design data due to, for example, the influence of etching or an aberration of an exposure unit. If such an actual pattern is to be superposed on the design data, a situation arises where matching suitable for evaluation can not be achieved due to the influence of the moved actual pattern. If the distance of a difference between the design data and the evaluation pattern is measured in such a case, an actual change of the shape to which a positional difference in matching is added is calculated as the distance of the difference.
Here, it is possible to provide in advance an evaluation region (region of interest: hereinafter simply referred to as “ROI”.) to prevent the inclusion of a pattern which has produced a positional difference so that matching is carried out only within this ROI. However, when the amount of the positional difference has changed due to a change of process conditions, questionable patterns may be contained in an assumed ROI. Moreover, in the case of a pattern having a complicated shape instead of the above-mentioned simple line pattern, it is not possible for a rectangular ROI to deal with such a pattern, and a problem arises in which the setting of the ROI itself becomes troublesome.